Fast LDO Handles a Wide Range of Load Currents and Load Capacitors, up to 100 mA and Over 1μF

This paper proposes a low dropout voltage regulator (LDO) that exhibits both fast response to load transients and the ability handle practically any capacitor. Starting from typical LDO topology, an error amplifier (EA) drives PMOS pass transistor passive feedback network, we inserted novel circuit, with input AC-coupled output connected directly gate. circuit creates inner loop able react quicker than main variations in voltage, appropriately inject or sink current to/from gate node. Moreover, helps reduce equivalent small-signal impedance at output, which turn reduces impact pole associated node has on stability. A compact implementation of this topology is presented paper: it combines proposed transient & frequency compensation high slew-rate EA. The resulting was integrated 130 nm standard CMOS technology. measurement results are good agreement simulations validate concept design. provides steady 1 V supply varying 1.2 1.5 going up 100 mA. Its maintain overshoot undershoot below 250 mV for C L = 0 under 60 $\text{C}_{\mathrm {L}} =1\,\,\mu \text{F}$ , when varies between notation="LaTeX">$\mu \text{A}$ mA \text{s}$ . requires only 6.2 quiescent occupies 0.018 mm 2 die area.